
`timescale 1ns / 1ns
module SpiControllerTest   ; 
 
  reg    iMiso   ; 
  reg  [7:0]  iMemData   ; 
  wire [7:0]  oMemData   ; 
  wire    oSclk   ; 
  reg  [17:0]  iStartAddress   ; 
  reg  [17:0]  iEndAddress   ; 
  wire    oMosi   ; 
  reg    iStartTransmit   ; 
  wire  oBusy   ; 
  reg    iClk   ; 
  wire  [17:0]  oMemAddress   ; 
  wire    oCs   ; 
  wire  oMemRdClk   ;
  wire  oMemWrClk   ;
  SpiController  
   DUT  ( 
      .iMiso (iMiso ) ,
      .iMemData (iMemData ) ,
      .oMemData (oMemData ) ,
      .oSclk (oSclk ) ,
      .iStartAddress (iStartAddress ) ,
      .iEndAddress (iEndAddress ) ,
      .oMosi (oMosi ) ,
      .iStartTransmit (iStartTransmit ) ,
      .oBusy (oBusy ) ,
      .iClk (iClk ) ,
      .oMemAddress (oMemAddress ) ,
      .oCs (oCs ) ,
      .oMemRdClk (oMemRdClk ) ,
      .oMemWrClk (oMemWrClk )
      ); 



// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ns, End Time = 10 us, Period = 20 ns
  initial
  begin
	  iClk  = 1'b0  ;
    repeat(499)
    begin
	    # 10 iClk  = 1'b1  ;
	    # 10 iClk  = 1'b0  ;
    end
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 10 us, Period = 0 ns
  initial
  begin
	  iStartTransmit  = 1'b0  ;
	  # 20 iStartTransmit  = 1'b1  ;
	  # 40 iStartTransmit  = 1'b0  ;
	 # 9940 ;
// dumped values till 10 us
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 10 us, Period = 0 ns
  initial
  begin
	  iStartAddress  = 18'b000000000000000000  ;
	 # 10000 ;
// dumped values till 10 us
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 10 us, Period = 0 ns
  initial
  begin
	  iEndAddress  = 18'b000000000000000010  ;
	 # 10000 ;
// dumped values till 10 us
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 10 us, Period = 0 ns
  initial
  begin
	  iMemData  = 8'b01011010  ;
	 # 10000 ;
// dumped values till 10 us
  end
  
// "Constant Pattern"
// Start Time = 0 ns, End Time = 10 us, Period = 0 ns
  initial
  begin
	  iMiso  = 1'b0  ;
	  # 400 iMiso  = 1'b1  ;
	  # 240 iMiso  = 1'b0  ;
	  # 240 iMiso  = 1'b1  ;
	  # 480 iMiso  = 1'b0  ;
	  # 240 iMiso  = 1'b1  ;
	  # 240 iMiso  = 1'b0  ;
	  # 600 iMiso  = 1'b1  ;
	  # 240 iMiso  = 1'b0  ;
	  # 240 iMiso  = 1'b1  ;
	  # 480 iMiso  = 1'b0  ;
	  # 240 iMiso  = 1'b1  ;
	  # 240 iMiso  = 1'b0  ;
	  # 600 iMiso  = 1'b1  ;
	  # 240 iMiso  = 1'b0  ;
	  # 240 iMiso  = 1'b1  ;
	  # 480 iMiso  = 1'b0  ;
	  # 240 iMiso  = 1'b1  ;
	  # 240 iMiso  = 1'b0  ;
  end

  initial
	#10000 $stop;
endmodule
